Composite pseudo associative cache with victim cache for mobile processors

Date
2010
Authors
Bobbala, Lakshmi Deepika
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Abstract

The purpose of this study is to design an efficient cache structure without increasing the area and power. A new cache structure called composite pseudo associative cache is designed by reconfiguring the structure of vway cache[1]. In this cache structure, way0 is implemented as traditional cache and the remaining ways are implemented as vway cache. This is based on the fact that the access of sets is unequal for different ways. To improve the hit rate further, victim cache has been added to the primary way of composite pseudo associative cache. The simulator is developed using C code. The trace files for seventeen Integer and floating point SPEC2006 benchmarks are retrieved. In order to validate the performance improvement, simulations were done for various cache sizes, block sizes and associativity using the trace files of SPEC2006 benchmarks. The simulations are done for both L1 and L2 trace data. The miss rate per kilo instruction (MPKI) is measured in all the simulations. It is compared for the traditional cache, vway cache, composite pseudo associative cache and composite pseudo associative cache with victim cache. Results proved that for some of the benchmarks, composite pseudo associative cache as well as composite pseudo associative cache with victim cache showed good performance improvement.

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Keywords
area, power, pseudo associative, victim, vway cache
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Department
Electrical and Computer Engineering