Performance tradeoffs of wide-bit CMOS nanometer adder topologies with applied leakage reduction techniques
The scaling of nanometer technology has had a major impact on the power dissipation of CMOS circuits. As transistor size decreases it has become apparent that leakage power is becoming a dominant fighting force against future technology. Low Power VLSI designs have focused their efforts on finding new design methodologies to reduce leakage power consumption. This research explores leakage power trends through the testing of leakage power reduction techniques in wide-bit adder topologies. Five different leakage reduction techniques were applied to arithmetic adder circuits for five bit sizes in three technology nodes. The leakage reduction techniques that were investigated in this research are: input vector control, dual voltage threshold, transistor stacking, long channel devices, and power gating. Four different adder topologies viz. the ripple carry adder, carry select adder, carry bypass adder, and carry look-ahead adder were designed for 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit addition. Each circuit was simulated using HSPICE for the 22nm, 32nm, and 45nm technology nodes. Predictive Technology Model (PTM) BSIM4 transistor models were used for all the simulations.
The results of the simulations were analyzed and evaluated against a 'standard' model with no applied leakage reduction technique. The trends in leakage power as a result of scaling and the effects of leakage techniques applied to nanometer technologies being explored by current IC designers were observed. The trade off of each applied leakage reduction technology was investigated. The overall results indicate that the use of long channel devices produced the optimized overall performance necessary for improving nanometer CMOS wide-bit adder circuits.