Adaptive instruction dispatching techiques for Simultaeous Multi Threading (SMT) processors
| dc.contributor.advisor | Lin, Wei-Ming | |
| dc.contributor.author | Debnath, Monobrata | |
| dc.contributor.committeeMember | John, Eugene | |
| dc.contributor.committeeMember | Lee, Byeong Kil | |
| dc.date.accessioned | 2024-02-09T20:49:38Z | |
| dc.date.available | 2024-02-09T20:49:38Z | |
| dc.date.issued | 2010 | |
| dc.description | This item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID. | |
| dc.description.abstract | Simultaneous Multi-Threading (SMT) provides an improved technique to improve resource utilization ability by sharing key datapath components among multiple independent threads. When critical resources are shared by multiple threads, effective use of these resources proves to be the most important factor in fully exploiting the system potential. The thread-level parallelism (TLP) present among the threads can be exploited intelligently to compensate the limited instruction level parallelism (ILP) present in each thread. This TLP is exploited further in the round robin dispatching with operand availability checking. The selection criteria for allocating Issue Queue (IQ) slots can be improved by not limiting the operand availability within the same thread. An effective scheduler for the SMT, named as Round robin with Operand Check, is proposed, that allocates IQ entries based on round robin principle within a cycle. This scheme will dispatch at most one instruction from each thread at its turn, instead of dispatching all the available instructions from a single thread. Our approach shows a 12% performance (IPC) improvement with a smaller IQ size (16). The proposed scheme is also much better matched with small-scale processors that require a smaller Issue Queue size. On the other hand, transient behaviors of various threads in terms of their execution parallelism can easily affect their utilization efficiency of these shared resources. To appropriate more resources to threads that are more active allows for better resource utilization and thus higher throughput. A real-time dynamic scheduler for the SMT is proposed, which dispatches instructions from threads based on thread-activeness information gathered in real time and dynamically adjusts the dispatching priorities accordingly. An extensive simulation shows a significant gain in system throughput by this technique. | |
| dc.description.department | Electrical and Computer Engineering | |
| dc.format.extent | 50 pages | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.isbn | 9781124385181 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12588/3368 | |
| dc.language | en | |
| dc.subject.classification | Computer engineering | |
| dc.title | Adaptive instruction dispatching techiques for Simultaeous Multi Threading (SMT) processors | |
| dc.type | Thesis | |
| dc.type.dcmi | Text | |
| dcterms.accessRights | pq_closed | |
| thesis.degree.department | Electrical and Computer Engineering | |
| thesis.degree.grantor | University of Texas at San Antonio | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |
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