Power Optimization Of Cyclic Redundancy Algorithms Using A New Search Technique For Look-Up Tables

In storage and transmission applications, preserving the integrity of data is of utmost importance, which is provided by Cyclic Redundancy Codes (CRC). CRC is an error detection technique used in digital, software and time division multiplexing applications to assist in error detection. CRCs are used for detecting corruption in data during production, transmission, processing and storage. The CRC calculations require limited resources and can be easily implemented. To support CRC code for high throughput standards at a reasonable frequency, the input bits must be read in parallel or in pipelined fashion.

In this thesis, different CRC algorithms are analyzed, and a power efficient CRC method is presented. To improve the performance of the cyclic codes, a new search algorithm for the look-up tables is introduced that aims to reduce the access time needed for obtaining the value from the lookup-tables. The performance of the algorithm is further improved by applying multi-threshold voltage techniques. The CRC algorithms are designed using SAED 90nm and Nangate 45nm process libraries. The simulations are performed for different corners at various voltages and temperatures. The data collected per simulation includes the power and delay values. A comparative analysis of different algorithms with the proposed algorithm is presented. Finally, the achieved results are compared with the previously published work.