Comparative Architectural Characterization of Three Different X86 Micro-architectures
The primary design objective for new leading-edge microprocessors has been performance. Each new generation of microarchitectures are better in terms of performance when compared to their predecessors. This research compares three different x86 microarchitectures based on their performance using SPEC CPU 2006 benchmarks. They are Intel Core (Core 2 Duo), Intel Ivy Bridge (core i5) and Intel Haswell (core i7). The applications of SPEC CPU2006 are compiled using the Intel C++/Fortran optimizing compiler and executed them using the reference data sets, on all three processors. The performance information was collected by using the Intel VTune Amplifier XE 2013 that takes advantage of the built in hardware performance counters to obtain accurate information on program behavior and its use of processor resources. The focus is on the instruction count, CPI, μops/instruction, branch prediction accuracy, and memory access behavior, which are the well-known indicators for
program performance problems. The impact of pre-fetching on processor performance is also studied by enabling prefetch option in all the three micro-architectures.
The clock cycles per instruction is estimated for all three processors. It was observed that the CPI of Core micro-architecture (core 2Duo) is higher than that of the CPI of Ivy Bridge and the CPI of Ivy Bridge are marginally higher than the CPI of Haswell. Relatively higher number
of μops/instruction could be observed in Haswell architecture and Ivy Bridge architectures than that of Core architecture. Instruction mix of three processors is characterized depending on the complexity of the ISA of their microarchitecture. The percentages of load, store and branches are observed to be higher in Core architecture than the ones in Ivy Bridge and Haswell. The hardware counters of the memory access behavior shows lower branch miss-prediction rates and higher cache hit-rates in Ivy Bridge and Haswell architecture than in Core architecture.