Ultra Low Power Circuits for Implantable Cardiac Devices

Today's pacemakers have more functionality and features than the pacemakers that were built a decade ago. These additional features come at the cost of increased power consumption which further leads to reduced battery life. A practical solution to reduce the power consumption of pacemakers is to reduce the power consumption of the circuits and systems that are in the pacemaker.

The primary objective of this research is to reduce the power consumption of specific circuits used in different functional blocks of a pacemaker. These power optimized circuits are expected to increase the overall battery life of pacemakers which in turn is expected to reduce the frequency of the surgical procedure needed to replace the pacemaker itself. The circuits investigated in this dissertation are: CMOS 8-bit analog to digital (ADC) converters, switched capacitor sample and hold circuits, FinFET based array multipliers and CMOS/FinFET based SRAM memory array.

The analog to digital converter proposed and designed in this dissertation consumes low power of 250nW and can operate at low voltages with a resolution of less than 0.9 mV. The proposed design occupies less than 66% of the layout area compared to other published results using the same technology node. This design has a peak-to-peak integral and differential nonlinearity variations of less than |0.5| LSB and a yield higher than 97.33%.

In a pacemaker, the sensed signal is sampled and held on a capacitor for further processing. Due to the low sampling frequency of the pacemaker, the charge on the capacitor must be held for longer duration and during this period the charge in the capacitor leaks continuously. This dissertation proposes two feedback cancellation and compensation switched capacitor sample and hold circuits which reduces the charge leakage during the long hold time in bio-medical devices and the dependency of rate of voltage drift on sampled input voltage level.

This dissertation also investigates four different FinFET based array multipliers performing 16x16 and 32x32 multiplication in various FinFET technology nodes. Performance metrics such as leakage power, average dynamic power, delay and energy consumption are measured. A comprehensive study is conducted to determine the suitability of these multipliers for implantable cardiac pacemakers.

Finally, three different SRAM memory cells in a 1Kx16 array using CMOS and FinFET based transistors are investigated in this dissertation. Power reduction techniques such as power gating, use of high threshold transistors, sub-threshold operation (up to data retention voltage) and combination of these three techniques are applied to reduce the leakage power consumption of the SRAM arrays. Performance metrics such as leakage power, delay and energy consumption are measured. A comprehensive study is conducted to determine the memory cell/array and the leakage reduction technique(s) suitable for implantable cardiac devices.