A Flexible Low Power Cyclic Redundancy Check Algorithm Using Reduced Lookup Tables in Parallel
| dc.contributor.advisor | John, Eugene | |
| dc.contributor.author | Barton, Dylan | |
| dc.contributor.committeeMember | Lin, Wei-Ming | |
| dc.contributor.committeeMember | Banerjee, Taposh | |
| dc.date.accessioned | 2024-01-25T22:34:12Z | |
| dc.date.available | 2024-01-25T22:34:12Z | |
| dc.date.issued | 2022 | |
| dc.description | This item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID. | |
| dc.description.abstract | Cyclic redundancy checks are widely used today to ensure data integrity. This is a method of checking data for corruption that is used in data communications, ethernet, and other broadcasting methods. This method of checking for data corruption is extremely flexible, and can be tailored to meet the requirements of many systems and devices. Using hardware or software, cyclic redundancy checks take an input message and does modular arithmetic with a generator polynomial specific to the task. When the arithmetic is done, these values are attached to the input message and sent to be checked upon arrival. Upon arrival, the arithmetic is done again, and if there is no remainder then the data is fine, otherwise an error will be detected. This research investigates and studies popular cyclic redundancy check algorithms and proposes a new flexible low power algorithm for 32, 64, and 128-bit input lengths. Each algorithm is implemented and simulated in Verilog using Vivado by Xilinx. Synopsys design compiler is then used to estimate the power, area, critical timing, and to implement clock and power gating on synthesis at 45nm technology node. Lastly, each design is realized using Cadence Innovus in 180nm technology node for the layout of each chip design. The proposed design is highly flexible and was able to decrease the area and power by over 20%. It also exhibited the least power and area for 64- and 128-bit input length when using clock and power gating. Lastly, because the proposed design uses a reduced number of lookup tables the memory requirement for the implementation is less compared to other designs. | |
| dc.description.department | Electrical and Computer Engineering | |
| dc.format.extent | 96 pages | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.isbn | 9798438756101 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12588/2482 | |
| dc.language | en | |
| dc.subject | CRC | |
| dc.subject | Cyclic Redundancy Check | |
| dc.subject | Lookup Tables | |
| dc.subject | Parallelism | |
| dc.subject | Reduced Lookup Table | |
| dc.subject.classification | Computer engineering | |
| dc.subject.classification | Electrical engineering | |
| dc.title | A Flexible Low Power Cyclic Redundancy Check Algorithm Using Reduced Lookup Tables in Parallel | |
| dc.type | Thesis | |
| dc.type.dcmi | Text | |
| dcterms.accessRights | pq_closed | |
| thesis.degree.department | Electrical and Computer Engineering | |
| thesis.degree.grantor | University of Texas at San Antonio | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |
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