VLSI Security and Performance Enghancement

dc.contributor.advisorLin, Wei-Ming
dc.contributor.authorWang, Qian
dc.contributor.committeeMemberQian, Chunjiang
dc.contributor.committeeMemberDuan, Lide
dc.date.accessioned2024-03-08T17:35:30Z
dc.date.available2024-03-08T17:35:30Z
dc.date.issued2017
dc.descriptionThis item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID.
dc.description.abstractHardware is the foundation of any security system. A growing number of security enhancement solutions are implemented in hardware due to the limitation of software implementation. However, hardware also faces a number of security threats. In today's global IC industry, a design house, an IP vendor, a CAD company, or a foundry could embed malicious Trojan components in an IC design, which (1) alters the computation, or (2) provides a back door for information leak. In the first half of this work, we achieve a Trojan component, which compromises the computation integrity of the OpenSPARC T2 processor with negligible area and power consumption overhead. In the second half of this work, we achieve a performance improvement technique for VLSI in the presence of performance variations. VLSI technology scaling has led to increasingly significant parametric variations from the manufacturing process and the runtime environment. Traditional worst case performance analysis and optimization techniques are overpessimistic and prevent VLSI from achieving further performance scaling. We apply a statistical performance analysis method Signal Probability Based Statistical Timing Analysis (SPSTA), and performance improvement for identified critical paths by Generalized Bypass Transform (GBT). Our experimental results based on ISCAS benchmark circuits show a 1.09X performance increasing while the tradeoff is an average of 1.35X area penalty.
dc.description.departmentElectrical and Computer Engineering
dc.format.extent72 pages
dc.format.mimetypeapplication/pdf
dc.identifier.isbn9780355166736
dc.identifier.urihttps://hdl.handle.net/20.500.12588/6122
dc.languageen
dc.subject.classificationElectrical engineering
dc.titleVLSI Security and Performance Enghancement
dc.typeThesis
dc.type.dcmiText
dcterms.accessRightspq_closed
thesis.degree.departmentElectrical and Computer Engineering
thesis.degree.grantorUniversity of Texas at San Antonio
thesis.degree.levelMasters
thesis.degree.nameMaster of Science

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