Design and implementation of low-power nano-scale hardware based crypto-systems

As the technology advances day by day, there is an essential need for a secured data transmission for exchanging information from one user to the other. Generally, data transmission techniques are achieved via private/public data networks. The transmission of data through these networks is not secured. Therefore, some kind of safety is needed for information exchange which is accomplished by encrypting the transmitted data. In this research a novel method is used in which hardware implementations of private/secret key encryption standards such as Advanced Encryption Standard (AES), Triple Data Encryption Standard (TDES) and Data Encryption Standard (DES) are integrated in a single silicon die of group centric Secured Information Sharing. This improves confidentiality, integrity and accuracy of the transmitted data. Advanced Encryption Standard is specified by National Institute of Standards (NIST) in 2001 as the specifications for encryption in electronic communication. It is also known as symmetric key algorithm as the encryption and decryption both are formulated using this single standard key. From the family of ciphers NIST selected three members of Rijndael family, each with key length of 128, 192 and 256 bits for each 128 bit block size as AES. For every key length a fixed number of rounds in AES are processed. For 128, 192 and 256 bits, 10, 12 and 14 rounds are executed respectively. In this research, AES 128 bits has been designed and implemented. Triple Data Encryption Standard (TDES) is a cipher algorithm where original Data Encryption Algorithm (DEA) or DES is applied three times. When DES was originally developed, it was sufficient to withstand the attacks using computer power of that era. However, with the remarkable increase in computing power, this algorithm was not complex enough to withstand the brutal attacks. To overcome this problem, Triple DES was proposed to offer high level of security without proposing any novel cipher algorithm. In this research all these three algorithms are implemented in Verilog and TSMC 65nm technology node. Xilinx ISE and Icarus Verilog are used for simulation of AES and DES. Cadence RTL Compiler is used to synthesize the design with minimum area. Finally the Graphic Database System (GDS) II layout of all the crypto cores and Top Module have been generated using Cadence Encounter.