Low Power FPGA Implementation of AES-256 Algorithm and Elliptic Curve Finite Field Operations

Low power design and embedded system security have become a major design consideration and challenge for today's digital designers. The importance of these two areas are apparent when considering applications such as Internet of Things (IoT), embeddable medical devices, aircraft flight control systems for unmanned systems and many other applications. Cryptographic algorithms required to provide these applications with data security are computationally intensive tasks not efficiently implemented in software. Hardware Description Languages (HDL) and Field Programmable Gate Arrays (FPGAs) provide an attractive option for digital designers for implementation of hardware-based embedded security which can significantly offload software for performing these computationally intensive cryptographic tasks. FPGAs are highly desirable for the implementation of cryptographic algorithms due to their flexibility, programmability, low end product life cycle, and fast time to market. The reprogrammable aspect of FPGAs is an attractive feature for implementing cryptographic functions that allows a hardware based solution the flexibility to change with today's ever changing security requirements. However, the reprogrammable feature of FPGAs comes at the expense of additional gates and thus will dissipate more power compared to their Application Specific Integrated Circuit (ASIC) counterparts. This thesis investigates system level techniques to achieve a low power cryptographic system. Low power system design techniques are investigated and implemented for both symmetric and asymmetric cryptographic algorithms. These algorithms include AES-256 and Elliptic Curve Finite Field Operations. The results of this research show that the use of low power FPGA design techniques can be used to provide a low power cryptographic solution for embedded systems.