Real-Time Modeling and Hardware-in-the-Loop Simulation of Cascaded Modular Multilevel Inverter for Photovoltaic Applications

Modular Multilevel converters (MMC) have many advantages over conventional voltage source converters. Some of those advantages are higher voltage levels up to 20kV, low THD, modularity and lower dV/dt per switch. However, MMC usually contain more number of switches compared to conventional converters. Therefore, offline simulation of MMC with higher number of switches can be time-consuming and can present challenges in simulating even few cycles. The Sim power system (SPS) is the main block set of Simulink to simulate electric circuits. It is based on state-space equations of power systems. It uses pre-calculation of all possible state-space matrices for all switch possibilities. Therefore, the simulation of circuits with significantly higher number of switches will not be easy and fast to simulate. One of the real-time simulators developed by OPAL-RT has introduced ARTEMIS solver, which enables to use State Space Nodal (SSN) solver. SSN of ARTEMIS separates the electric circuit into small groups and finds the associated equations for each one. While the Sim Power System is trying to solve the entire inverter circuit, SSN divides this complicated network into small groups and solves for each using SSN.

This dissertation demonstrates the real-time simulation of two modular multilevel inverters which are cascaded H-bridge (CHB) multilevel inverter and cascaded Neutral Point Clamped (CNPC) multilevel inverter. ARTEMIS SSN solver created by OPAL-RT is used as a solver to make simulation faster and to be able to use a greater number of switches without overloading the cache memory. These modular multilevel inverters are well suited to PV applications since they require having separate dc sources which can be obtained from solar PV arrays.

In this dissertation, five-ports cascaded NPC multilevel inverter is modeled in real-time simulation by presenting software-in-the-loop, hardware-in-the-loop, and power hardware- in-the-loop results. Scaling up the system in OPAL-RT reduced the simulation time since it has faster simulation capability. Moreover, it reduced the whole system cost since any changes can be tested in real-time before building the actual hardware. Hardware-in-the-loop results proved that five-ports cascaded NPC multilevel inverter has higher voltage levels (21 levels), low THD (6.18%), modularity and lower dV/dt per switch. Power hardware-in-the-loop results showed the actual response of the five-ports CNPC model when connected to an R-L load. This cascaded NPC multilevel inverter can be used as a dc-ac stage for photovoltaic applications.