Low power implementation of an AES 128-bit encryption
| dc.contributor.advisor | John, Eugene Britto | |
| dc.contributor.author | Mahadevan, Sreeram Anikode | |
| dc.contributor.committeeMember | Krishnan, Ram | |
| dc.contributor.committeeMember | Lee, Junghee | |
| dc.date.accessioned | 2024-01-26T16:48:11Z | |
| dc.date.available | 2024-01-26T16:48:11Z | |
| dc.date.issued | 2015 | |
| dc.description | This item is available only to currently enrolled UTSA students, faculty or staff. To download, navigate to Log In in the top right-hand corner of this screen, then select Log in with my UTSA ID. | |
| dc.description.abstract | Not every innovative design/technology initially meets all of its design goals. Though there may be versions which complies with all of these parameters, many a times there occurs variants of these design/technology which accomplishes one or more parameter while comprising with one or the other. "The Advanced Encryption Standard (AES), also known as Rijndael, is a specification for the encryption of electronic data established by the U.S. National Institute of Standards and Technology (NIST) in 2001". Many speed and security optimized variants of this architecture were developed, since most among them were employed over purely software platform. Silicon die design and validation cost forced early hardware implementations to be keen on area optimization, later the focus was changed to other parameters such as maximizing throughput with comprising area, power etc. This work concentrates on reducing the present power elements of the hardware implementations without losing the integrity or compromising the security, and make the architecture compatible for Low-power applications, where execution rate is not much of a consideration. Three variants of codes were synthesized and analyzed using Synopsis Design compiler with 45nm NanGate Open Cell library and TMSC 180nm technology nodes. The results obtained were promising when compared with results already published. | |
| dc.description.department | Electrical and Computer Engineering | |
| dc.format.extent | 86 pages | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.isbn | 9781339309477 | |
| dc.identifier.uri | https://hdl.handle.net/20.500.12588/2528 | |
| dc.language | en | |
| dc.subject | 128-bit | |
| dc.subject | Advanced Encryption Standard | |
| dc.subject | Low-power | |
| dc.subject.classification | Computer engineering | |
| dc.subject.classification | Computer science | |
| dc.subject.lcsh | Computer input-output equipment -- Design and construction | |
| dc.subject.lcsh | Data encryption (Computer science) | |
| dc.title | Low power implementation of an AES 128-bit encryption | |
| dc.type | Thesis | |
| dc.type.dcmi | Text | |
| dcterms.accessRights | pq_closed | |
| thesis.degree.department | Electrical and Computer Engineering | |
| thesis.degree.grantor | University of Texas at San Antonio | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |
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